1. Field of the Invention
Embodiments of the present invention relate generally to memory devices and more specifically, in one or more embodiments, to non-volatile memory devices.
2. Description of the Related Art
Processor-based systems, such as computers, typically include one or more memory devices to provide storage capability for the system. Generally, system memory is provided in the form of one or more memory devices and generally includes both random access memory (RAM) and read-only memory (ROM). System RAM is typically large and volatile and provides the system's main memory. Static RAM and Dynamic RAM are commonly employed types of random access memory. In contrast, system ROM is generally small and includes non-volatile memory for storing initialization routines and identification information. One common type of read-only memory is electrically-erasable read only memory (EEPROM) in which an electrical charge may be used to program and/or erase data in the memory. Although EEPROM can be erased and re-programmed multiple times, they are still described as “read-only memory” as, generally speaking, the reprogramming process is generally infrequent, comparatively slow, and often does not permit random access writes to individual memory locations (which are possible when reading a ROM).
Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks. Flash memory is often employed in personal computer systems in order to store the Basic Input Output System (BIOS) program such that it can be easily updated. Flash memory is also employed in wireless electronic devices, because it enables the manufacturer to support new communication protocols as they become standardized and provides the ability to remotely upgrade the devices for enhanced features.
A typical flash memory includes a memory array having a large number of memory cells arranged in rows and columns. The memory cells are generally grouped into blocks such that groups of cells can be programmed or erased simultaneously. Each of the memory cells usually includes a floating-gate field-effect transistor capable of holding a charge, although other charge storage nodes could be used, such as charge traps such as SONOS devices. Floating gate memory cells differ from standard MOSFET designs in that they include an electrically isolated gate, referred to as the “floating gate,” in addition to the standard control gate. The floating gate is generally formed over the channel and separated from the channel by a dielectric (e.g., oxide) layer. The control gate is formed directly above the floating gate and is separated from the floating gate by another dielectric (e.g., oxide) layer. A floating gate memory cell stores information by holding electrical charge within the floating gate. By adding or removing charge from the floating gate, the threshold voltage of the cell changes, thereby defining whether this memory cell is programmed or erased.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a select line, which is often referred to as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a transfer line, which is commonly referred to as a bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word-select line connected to a control gate of a memory cell. In addition, the word-select lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the bit line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the bit lines.
In scaling NAND flash memory with today's ever-decreasing device geometries, the dielectric layers of the memory cells are becoming increasingly thinner. Additionally, the thinner dielectric oxide layers help to reduce the voltage level(s) associated with program and erase the cells. However, because the dielectric layers have a reduced thickness, current between the control gate and the substrate may be introduced during the program and erase operations. The current may be especially prevalent in memory cells adjacent to the source select gates and the drain select gates during an erase operation and is induced because of the high electrical field when an erase voltage is applied to the substrate and the low gate coupling ratio of the dielectric layer between the control gate and the floating gate.
Embodiments of the present invention may be directed to one or more of the problems set forth above.